Director and Head of Trading Technology at Quant Capital Consulting
FPGA ENGINEER – ULTRA-LOW LATENCY SYSTEMSLocation: London (Hybrid: 4 days onsite)Sector: Quant Trading / High-Performance ComputingQuant Capital is partnering with a global trading firm building a greenfield FPGA team focused on low-latency, high-throughput hardware systems. This small, senior group will deliver high-speed compute infrastructure integrated directly into trading, research, and networking pipelines.
What You’ll Be Doing
Designing and implementing latency-optimised FPGA systems in Verilog/SystemVerilog
Developing high-speed modules (PCIe, Ethernet, DDR/QDR) with deep pipelining
Using simulation and formal tools (Verilator, Cocotb, etc.) for validation
Working across teams (ASIC, software, infra) to co-design tightly coupled platforms
Contributing to tooling, flow, and potentially DSL extensions
What We’re Looking For
Strong RTL skills with experience building complex, optimised designs
Programming skills, C, C++ or similar
Solid grasp of timing closure, datapath design, and hardware-level performance tuning
Familiar with toolchains (Vivado, Quartus) and debugging workflows
Comfortable working close to hardware and owning the full development cycle
Interest in improving hardware workflows or applying high-level techniques
Bonus
Background in trading systems, signal processing, or networking
Experience with formal verification and/or hardware DSLs
Knowledge of FPGA-based networking acceleration
Why Join?
Build from scratch with a team driving real strategy and architectural decisions
Work across the full lifecycle, from concept to deployment
Deep technical ownership, minimal overhead, and real impact
Collaborate with top engineers in a no-bureaucracy culture
All enquiries handled in strict confidence. Your profile will only be shared with your permission.
Additional Details
Seniority level : Mid-Senior level
Employment type : Full-time
Job function : Information Technology
Industries : Capital Markets and Financial Services
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