<?xml version="1.0" encoding="utf-8"?>
<rss version="2.0">
  <channel>
    <title>Principal FPGA Design Engineer - Oxfordshire - Morgan McKinley RSS Feed</title>
    <link>https://jobs.co.uk/job/principal-fpga-design-engineer-oxfordshire-morgan-mckinley--ba5a03e1-0817-484f-b42d-f8289674e0d7</link>
    <description>RSS feed for Principal FPGA Design Engineer - Oxfordshire at Morgan McKinley.</description>
    <language>en-gb</language>
    <lastBuildDate>Thu, 01 Oct 2026 21:49:46 GMT</lastBuildDate>
    <item>
      <title>Principal FPGA Design Engineer - Oxfordshire - Morgan McKinley</title>
      <link>https://jobs.co.uk/job/principal-fpga-design-engineer-oxfordshire-morgan-mckinley--ba5a03e1-0817-484f-b42d-f8289674e0d7</link>
      <guid>https://jobs.co.uk/job/principal-fpga-design-engineer-oxfordshire-morgan-mckinley--ba5a03e1-0817-484f-b42d-f8289674e0d7</guid>
      <pubDate>Thu, 01 Oct 2026 11:53:08 GMT</pubDate>
      <description>Location: Oxford | Salary: 10000-500000 Annual | Type: Permanent | Role: Principal FPGA Design Engineer Location: Oxfordshire Package: £80k - £120k + Bonus + Generous Benefits About the Business: We are partnering with a pioneering UK technology innovator developing next-generation medical device technologies. Operating globally, they combine hardware, custom silicon, and complex data processing to transform global healthcare and scientific research. Role Overview: A hands-on technical leadership and mentorship position, owning the architecture and delivery of high-throughput FPGA subsystems. You will drive designs across the full lifecycle-from initial requirements through RTL implementation, custom-ASIC bring-up, lab validation, and product release. Key Responsibilities:  System Architecture: Lead FPGA subsystem architecture for complex data platforms. RTL and Verification: Design/verify digital RTL (SystemVerilog/Verilog) using AMD/Xilinx toolchains. Optimization: Maximize throughput, power efficiency, resource usage, and timing closure. Integration: Collaborate with ASIC, FW, and SW teams to support board bring-up. Leadership: Champion CI/CD automation and mentor mid/senior hardware engineers.  What We Need:  Proven full-lifecycle FPGA design ...</description>
      <category>Permanent</category>
    </item>
  </channel>
</rss>