<?xml version="1.0" encoding="utf-8"?>
<rss version="2.0">
  <channel>
    <title>ASIC Engineer - eTeam Workforce Limited RSS Feed</title>
    <link>https://jobs.co.uk/job/asic-engineer-eteam-workforce-limited--5032113c-fb69-4325-acd5-96e811276787</link>
    <description>RSS feed for ASIC Engineer at eTeam Workforce Limited.</description>
    <language>en-gb</language>
    <lastBuildDate>Thu, 06 Aug 2026 11:35:03 GMT</lastBuildDate>
    <item>
      <title>ASIC Engineer - eTeam Workforce Limited</title>
      <link>https://jobs.co.uk/job/asic-engineer-eteam-workforce-limited--5032113c-fb69-4325-acd5-96e811276787</link>
      <guid>https://jobs.co.uk/job/asic-engineer-eteam-workforce-limited--5032113c-fb69-4325-acd5-96e811276787</guid>
      <pubDate>Wed, 05 Aug 2026 11:51:35 GMT</pubDate>
      <description>Location: Farnborough | Salary: 350.00-350.00 Daily | Type: Contract | Title: ASICS Engineering Duration: Sep 7, 2026 - Mar 5, 2027 Hours Per Week: 37.00  Location: Farnborough TECHNICAL SKILLS: Must Have:  5+ year of RFIC work experience AMS simulations Experience of verification simulations of complete transceiver chains RF -andgt; Analogue Verilog-A Verilog-AMS  Nice To Have:  Digital verification skills  The senior engineer will take on the verification of full Rx and Tx chains of an on-going design.  They will help setup and debug simulation testbenches, report compliance to spec and validate device register controls for test.  The tasks will include:  Review of block specifications. Simulation and reporting compliance to specifications. Root cause any specification failures. Liaising with the chip lead to integrate the designs. Presentation of design for block-level reviews.</description>
      <category>Contract</category>
    </item>
  </channel>
</rss>